SDD 2010 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

Troubleshooting how and why systems and circuits fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, correcting the design function, failure mode learning for R&D, or just getting a working first prototype. This detective work is however very tricky. Sources of difficulty include circuit and system complexity, packaging, limited physical access, shortened product creation cycle and time-to-market, the traditional focus on only pass/fail testing and missing tool and equipment capabilities. New and efficient solutions for debug and diagnosis have a much needed and highly visible impact on productivity.

The topics of interest include, but are not limited to, the following:

Debug Techniques and Methodologies	Microprocessor, FPGA, IP, SOC Debug
Design and Synthesis for Debug	Infrastructure IP for SDD
DFT Reuse for Debug and Diagnosis	System Level Debug & Diagnosis
Debug & Diagnosis Architectures	Manufacturing & Prototype Environment
Tools	Equipment Impact and Techniques
Debug Standardization	Cross-geography turn-on, debug & diagnosis issues
SDD vs. Yield & TTM	Digital / Analog Turn-on
Case studies

Submissions

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The workshop objective is to facilitate a valuable interactive information exchange. Contributions ranging from extended abstracts to full papers are acceptable for submission. Proposals that describe open issues, industry/technology needs or opinions are also welcome.

Length Guideline: ranging from a one page, extended abstract up to 8 pages.
Submissions due: November 6th, 2009
Acceptance Notification: November 20th, 2009
Final papers for inclusion into informal proceedings: March 3rd, 2010

Proposals for discussion panels and other special sessions are also invited. Please submit a one page abstract for these to the web site or contact the Program Co-chairs.

Key Dates

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Paper Submission deadline: November 6, 2009
Notification of Acceptance: November 20, 2009
Camera-Ready Material due date: March 3, 2010

Additional Information

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General Information
Bart Vermeulen
NXP Semiconductors
bart.vermeulen@nxp.com

Submission & Program Information
Christian Boit
Berlin University of Technology
christian.boit@tu-berlin.de

Al Crouch
ASSET Intertech
acrouch@asset-intertech.com

Committees

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General Chair
B. Vermeulen – NXP Semiconductors

Program Co-chairs
C. Boit – TU Berlin
A. Crouch – ASSET Intertech

Asian Liaison
K. Hatayama – STARC

European Liaison
D. Appello – STMicroelectronics

North-American Liaison
T. McLaurin – ARM

University Liaison
Z. Zilic – McGill Univ.

Electronic Media
I. Bayraktaroglu – Sun

Local Arrangements
P. Cheung – Imperial College London
N. Nicolici – McMaster Univ.

Program Committee
M. Abadir – Freescale
M. Abramovici – DAFCA
B. Benware – Mentor Graphics
V. Bertacci – Univ. of Michigan
S. Blanton – Carnegie Mellon Univ.
B. Cory – nVidia
B. Eklow – Cisco Systems
J. Giacobbe – Intel
R. Guo – Mentor Graphics
S. Gupta – USC
I. Hartanto – Xilinx
Y-C. Hsu – SpringSoft
D. Josephson – Intel
R. Kapur – Synopsys
H. Kerkhoff – Univ. Twente
C. Metra – Univ. Bologna
A. Orailoglu – UCSD
S. Pappalardo – STMicroelectronics
P. Prinetto – Poli. Di Torino
M. Renovell – LIRMM
M.S. Reorda – Poli. Di Torino
N. Stollon – HDLdynamics
C. Sul – Silicon Image
J. Tyzer – U. Poznan
S. Venkataraman – Intel
Z. Zilic – McGill Univ.

Steering Committee
R. Aitken – ARM
E.J. Marinissen – IMEC
F. Muradali – National Semiconductor
M. Ricchetti – AMD (chair)
Y. Zorian – Virage Logic

For more information, visit us on the web at: http://www.sdd-online.org

The 6th IEEE International Workshop on Silicon Debug and Diagnosis (SDD 2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).